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19-3290; Rev 0; 7/04
KIT ATION EVALU ILABLE AVA
1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers
General Description
The MAX8563/MAX8564 ultra-low-output dual and triple LDO controllers allow flexible and inexpensive point-ofload voltage conversion in motherboards, desknotes, notebooks, and other applications. Both parts feature a 0.5V reference voltage with 1% accuracy providing tight regulation of the output voltage. The MAX8563 has three n-channel MOSFET controller outputs, and the MAX8564 has two controller outputs. Each controller output is adjustable from 0.5V to 3.3V when VDD = 12V and between 0.5V and 1.8V when VDD = 5V. Each output is independently enabled and asserts a POK signal when the output reaches 94% of the set value. Each output is protected against a soft short-circuit condition by an undervoltage comparator that disables the output when it drops to under 80% of the set voltage for more than 50s. For a catastrophic short condition, the regulators are shut down immediately if the output drops below 60% of the set voltage. The MAX8563 is available in a 16-pin QSOP package, and the MAX8564 is available in a 10-pin MAX (R) package. MAX8563: 3 Outputs MAX8564: 2 Outputs 1% Feedback Regulation Adjustable Output Voltage Down to 0.5V Can Use Ceramic Output Capacitors Wide Supply Voltage Range Permits Operation from 5V or 12V Rails Individual Enable Control and POK Signal Allows Sequencing Overload Protection Against Soft-Short Condition Undervoltage Short-Circuit Protection Drive n-Channel MOSFETs
Features
MAX8563/MAX8564
Ordering Information
PART MAX8563EEE MAX8564EUB TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 16 QSOP 10 MAX
Applications
Motherboards Dual/Triple Power Supplies Desknotes and Notebooks Graphic Cards Ultra-Low-Dropout Voltage Regulators Low-Voltage DSP, P, and Microcontroller Power Supplies
1.8V 5% IN C1
Pin Configurations appear at end of data sheet.
MAX is a registered trademark of Maxim Integrated Products, Inc.
Typical Operating Circuit
5V OR 12VIN 1.2V 5% IN C2 C3
Q1 OUT1 1.5V/1.5A C4 R1 R4 FB1 R3 OFF POK1 3.3V 5% IN C8 ON EN1 POK1 GND DRV2 R5 FB2 ON EN2 POK2 OFF POK2 C5
R2 DRV1 VDD C6
Q2 OUT2 1.05V/3A C7
MAX8563
N.C. Q3 C10 OUT3 2.5V/2A* C9 R8 FB3 R9 R7 DRV3
N.C.
R6
POK3 ON EN3 OFF
POK3
*2.5V OUTPUT ONLY WITH VDD = 12V
________________________________________________________________ Maxim Integrated Products
1
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1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers MAX8563/MAX8564
ABSOLUTE MAXIMUM RATINGS
VDD to GND ............................................................-0.3V to +14V DRV1, DRV2, DRV3, EN1, EN2, EN3 to GND............................................-0.3V to (VDD + 0.3V) FB1, FB2, FB3, POK1, POK2, POK3 to GND ...........-0.3V to +6V Continuous Power Dissipation (TA = +70C) 10-Pin MAX (derate 5.6mW/C above +70C) ........444.4mW 16-Pin QSOP (derate 8.3mW/C above +70C)........666.7mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = VEN1 = VEN2 = VEN3 = 5V, VGND = 0V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER GENERAL VDD Voltage Range VDD Undervoltage-Lockout Threshold VDD Quiescent Current VDD Shutdown Current LDOs FB_ Accuracy FB_ Input Bias Current DRV_ Soft-Start Charging Current DRV_ Max Sourcing Current DRV_ Max Sinking Current DRV_ Max Voltage FB_ Slow Short-Circuit Threshold FB_ Fast Short-Circuit Threshold Slow Short-Circuit Timer FB_ to DRV_ Transconductance LOGIC EN_ Input Low Level EN_ Input High Level EN_ Input Leakage Current VEN_ = 0 and VDD, VDD = 13.2V TA = +25C TA = +85C 1.3 -0.1 0.001 +0.1 0.7 V V A 0.115 VFB_ = 0.45V VFB_ = 0.6V TA = 0C to +85C TA = -40C to +85C TA = 0C to +85C TA = -40C to +85C 4 3 3 1.8 4.7 8.0 400 300 50 0.24 0.460 10.9 7 7 TA = 0C to +85C TA = -40C to +85C TA = +25C TA = +85C 0.494 0.489 -100 -8 100 0.5 0.504 0.509 +100 V nA A mA mA V mV mV s Mho Rising, 200mV hysteresis (typ) VEN_ = VDD = 12V (MAX8563) VEN_ = VDD = 12V (MAX8564) EN1 = EN2 = EN3 = GND, VDD = 12V 4.5 3.56 3.76 930 660 13.2 4.00 1600 1200 25 V V A A CONDITIONS MIN TYP MAX UNITS
VDD = 5V, VFB_ = 0.46V VDD = 13.2V, VFB_ = 0.46V Measured at FB_ (falling) Measured at FB_ (falling)
2
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1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers
ELECTRICAL CHARACTERISTICS (continued)
(VDD = VEN1 = VEN2 = VEN3 = 5V, VGND = 0V, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER POK_ Threshold Falling POK_ Threshold Rising at Startup POK_ Output Low Level POK_ Output High Leakage CONDITIONS Measured at FB_ (falling) Measured at FB_ (rising) Sinking 1mA, VDD = 4.5V, VFB_ = 0.4V VDD = 5.5V TA = +25C TA = +85C 0.001 MIN 425 455 TYP 440 470 MAX 455 485 0.1 0.1 UNITS mV mV V A
MAX8563/MAX8564
Note 1:
Specifications are production tested at TA = +25C. Maximum and minimum specifications over temperature are guaranteed by design.
Typical Operating Characteristics
(Circuit of Figure 1, TA = +25C.)
OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX8563 toc01
OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX8563 toc02
OUTPUT VOLTAGE vs. OUTPUT CURRENT
2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0 VOUT3 VDD = 12V
MAX8563 toc03
1.6 VDD = 5V 1.5 OUTPUT VOLTAGE (V) 1.4 1.3 1.2 1.1 1.0 VOUT1
2.6 VDD = 12V 2.4 OUTPUT VOLTAGE (V) 2.2 2.0 1.8 1.6 1.4 VOUT1 VOUT3
OUTPUT VOLTAGE (V)
VOUT1
VOUT2
1.2 1.0 1.0
VOUT2 1.4 1.8 2.2 2.6 3.0 3.4
VOUT2 0.5 1.0 1.5 2.0 2.5 3.0
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
OUTPUT CURRENT (A)
FEEDBACK VOLTAGE vs. TEMPERATURE
MAX8563 toc04
PSRR vs. FREQUENCY
90 80 70 PSRR (dB) 60 50 40 30 20 VDRV2 100 1k 10k 100k VIN2 VOUT1 = 1.5V VIN1 = 2V LOAD = 1.25 VDD = 12V
MAX8563 toc05
LOAD TRANSIENT
MAX8563 toc06
0.5000 VDD = 5V 0.4998 FEEDBACK VOLTAGE (V) 0.4996 0.4994 0.4992 0.4990 0.4988 0.4986 -40 -15 10 35 60 VDD = 12V
100
IOUT2 2A/div 0 VOUT2 20mV/div AC-COUPLED
200mV/div AC-COUPLED
10 0 85 TEMPERATURE (C) FREQUENCY (Hz)
VDD = 12V FIGURE 1, C7 = 100F 6TPE100MI 10s/div
2V/div 0
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1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers MAX8563/MAX8564
Typical Operating Characteristics (continued)
(Circuit of Figure 1, TA = +25C.)
POWER-ON SEQUENCING WITH VDD
MAX8563 toc07
POWER-ON SEQUENCING WITH VIN
MAX8563 toc08
VDD
20V/div 0 2V/div 0
VDD
ENABLE CONFIGURED AS SHOWN IN FIGURE 4 RD = 100k, RE = 4k
20V/div 0 2V/div 0
VOUT1
VIN1
VIN1
2V/div 0
VOUT1
2V/div 0 2V/div 0
VPOK1
2V/div VPOK1 0
20ms/div
10ms/div
ENABLE-ON SEQUENCING
MAX8563 toc09
SHORT-CIRCUIT PROTECTION
MAX8563 toc10
VIN1
2V/div 0 2V/div IOUT1 5A/div 0 VOUT1 1V/div 0
EN1 0 VOUT1 2V/div 0 2V/div VPOK1 0
VDRV1 2V/div 0 20s/div
20ms/div
4
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1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers
Functional Diagram
VDD VL 0.5V REF GND MAX8563 MAX8564 UVLO
MAX8563/MAX8564
VDD VDD EN1 VL POK1 0.5V GM DRV1
POK COMPARATOR
LDO CONTROLLER 1
FB1
EN2 POK2 LDO CONTROLLER 2
DRV2 FB2
EN3 POK3 LDO CONTROLLER 3
DRV3 FB3
Pin Description
PIN NAME MAX8563 DRV1 MAX8564 DRV1 FUNCTION Output n-MOSFET Drive. Drives the gate of an external n-channel MOSFET to regulate output 1. DRV1 is internally pulled to ground when EN1 is logic low. Connect an external series RC circuit for compensation. See the Stability Compensation section. Feedback Input for Output 1. Connect to the center of a resistor-divider between output 1 and GND to set the output voltage of output 1. The feedback regulation voltage is 0.500V. See the Output Voltage Setting section. Enable Control for Output 1. Drive logic high to enable output 1, or logic low to disable the output. Connect to VDD for always-on operation. Output 1 Power-Good Signal. Open-drain output pulls low when output 1 is 12% below the nominal regulated voltage. Ground Output 2 Power-Good Signal. Open-drain output pulls low when output 2 is 12% below the nominal regulated voltage. No Internal Connection
1
2
FB1
FB1
3 4 5
EN1 POK1 GND --
EN1 POK1 GND POK2 --
6 N.C.
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1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers MAX8563/MAX8564
Pin Description (continued)
NAME PIN MAX8563 -- 7 DRV3 -- MAX8564 EN2 Enable Control for Output 2. Drive logic high to enable output 2, or logic low to disable the output. Connect to VDD for always-on operation. Output 3 n-MOSFET Drive. Drives the gate of an external n-channel MOSFET to regulate output 3. DRV3 is internally pulled to ground when EN3 is logic low. Connect an external series RC circuit for compensation. See the Stability Compensation section. Feedback Input for Output 2. Connect to the center of a resistor-divider between output 2 and GND to set the output voltage of output 2. The feedback regulation voltage is 0.500V. See the Output Voltage Setting section. Feedback Input for Output 3. Connect to the center of a resistor-divider between output 3 and GND to set the output voltage of output 3. The feedback regulation voltage is 0.500V. See the Output Voltage Setting section. Output 2 n-MOSFET Drive. Drives the gate of the external n-channel MOSFET to regulate output 2. DRV2 is internally pulled to ground when EN2 is logic low. Connect an external series RC circuit for compensation. See the Stability Compensation section. Enable Control for Output 3. Drive logic high to enable output 3, or logic low to disable the output. Connect to VDD for always-on operation. +5V or +12 Supply Input. Connect to external +5V or +12V supply rail. Bypass with a 0.1F ceramic or larger capacitor. Output 3 Power-Good Signal. Open-drain output pulls low when output 3 is 12% below the nominal regulated voltage. No Internal Connection Output 2 Power-Good Signal. Open-drain output pulls low when output 2 is 12% below the nominal regulated voltage. Enable Control for Output 2. Drive logic high to enable output 2, or logic low to disable the output. Connect to a VDD for always-on operation. Feedback Input for Output 2. Connect to the center of a resistor-divider between output 2 and GND to set the output voltage of output 2. The feedback regulation voltage is 0.500V. See the Output Voltage Setting section. Output 2 n-MOSFET Drive. Drives the gate of the external n-channel MOSFET to regulate output 2. DRV2 is internally pulled to ground when EN2 is logic low. Connect an external series RC circuit for compensation. See the Stability Compensation section. +5V or +12V Supply Input. Connect to an external +5V or +12V supply rail. Bypass with a 0.1F ceramic or larger capacitor. FUNCTION
-- 8 FB3
FB2
--
-- 9 EN3 -- 10 POK3 11 12 13 N.C. POK2 EN2
DRV2
-- VDD -- -- -- --
14
FB2
--
15
DRV2
--
16
VDD
--
6
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1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers
Typical Application Circuits
MAX8563: Triple Output
MAX8563/MAX8564
1.8V 5% IN C1
5V OR 12VIN
1.2V 5% IN C2 Q1 OUT1 1.5V/1.5A C4 R1 R4 FB1 R3 ON OFF EN1 DRV2 R5 C5 C3
R2 DRV1 VDD C6
Q2 OUT2 1.05V/3A C7
MAX8563
FB2 ON
POK1 3.3V 5% IN C8
POK1
EN2
OFF
GND Q3 OUT3 2.5V/2A* C9 R8 FB3 R9 C10
POK2
POK2
N.C. R7 DRV3
N.C.
R6
POK3 ON EN3 OFF
POK3
*2.5V OUTPUT ONLY WITH VDD = 12V
Figure 1. MAX8563 Typical Application Circuit
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1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers MAX8563/MAX8564
Typical Application Circuits (continued)
MAX8564: Dual Output
1.8V 5% IN C15 C11 Q4 OUT1 1.5V/1.5A C14 R16 FB1 R17 ON OFF POK1 EN1 POK1 GND C20 R18 DRV1 VDD R15 DRV2 R14 C18 C12 OUT2 1.05V/3A Q5 5V OR 12VIN 1.2V 5% IN C17
MAX8564
FB2 ON EN2 POK2 R13 OFF POK2
Figure 2. MAX8564 Typical Application Circuit
MAX8563 External Component List
COMPONENTS QTY DESCRIPTION 2.2F, 10V X5R ceramic capacitors (optional 100F, 18m, 6.3V aluminum electrolytic, Sanyo GTPE100MI in parallel) 0.1F, 16V X7R ceramic capacitor 100F, 18m, 6.3V aluminum electrolytic capacitors Sanyo GTPE100MI 1F, 16V X7R ceramic capacitors Dual n-channel MOSFETs, 30V, 18m Vishay Si4922DY N-channel MOSFET, 30V, 50m Fairchild Semiconductor FDD6630A 665 1% resistor 620 5% resistor 332 1% resistor 390 5% resistor 182 1% resistor 165 1% resistor 910 5% resistor 1k 1% resistor 249 1% resistor
MAX8564 External Component List
COMPONENTS QTY C11 C12, C14 1 2 DESCRIPTION 0.1F, 16V X7R ceramic capacitor 100F, 18m, 6.3V aluminum electrolytic capacitors Sanyo GTPE100MI 2.2F, 10V X5R ceramic capacitors (optional 100F, 18m, 6.3V aluminum electrolytic, Sanyo GTPE100MI in parallel) 1F, 16V X7R ceramic capacitors Dual n-channel MOSFETs, 30V, 18m Vishay Si4922DY 165 1% resistor 182 1% resistor 390 5% resistor 665 1% resistor 332 1% resistor 620 5% resistor
C1, C3, C8
3
C2 C4, C7, C9 C5, C6, C10 Q1/Q2 (Dual) Q3 R1 R2 R3 R4 R5 R6 R7 R8 R9
1 3 3 1 1 1 1 1 1 1 1 1 1 1
C15, C17
2
C18, C20 Q4/Q5 (Dual) R13 R14 R15 R16 R17 R18
2 1 1 1 1 1 1 1
8
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1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers
Detailed Description
The MAX8563/MAX8564 triple and dual LDO controllers allow flexible and inexpensive voltage conversion by controlling the gate of an external n-MOSFET in a source-follower configuration. The MAX8563/MAX8564 consist of multiple identical LDO controllers. Each LDO controller features an enable input (EN_) and a powerOK output (POK_). The MAX8563/MAX8564 also include a 0.5V reference, an internal regulator, and an undervoltage lockout (UVLO). The transconductance amplifier measures the feedback voltage on FB_ and compares it to an internal 0.5V reference connected to the positive input. If the voltage on FB_ is lower than 0.5V, the current output on the gate-drive output DVR_ is increased. If the voltage on FB_ is higher than 0.5V, the current output on the gate-drive output is decreased.
MAX8563/MAX8564
VIN_
Q1 OUT1 COUT CC
RC DRV_
MAX8563 MAX8564
Figure 3. Soft-Start and Compensation Schematic
Bias Voltage (VDD), UVLO, and Soft-Start
The MAX8563/MAX8564 bias current for internal circuitry is supplied by VDD. The VDD voltage range is from 4.5V to 13.2V. If VDD drops below 3.76V (typ), the MAX8563/ MAX8564 assume that the supply and reference voltages are too low and activate the UVLO circuitry. During UVLO, the internal regulator (VL) and the internal bandgap reference are forced off, DRV_ is pulled to GND, and POK_ is pulled low. Before any internal startup circuitry is activated, VDD must be above the UVLO threshold. After UVLO indicates that VDD is high enough, the internal VL regulator, the internal bandgap reference, and the bias currents are activated. If EN_ is logic-high after the internal reference and bias currents are activated, then the corresponding DRV_ output initiates operation in soft-start mode. Once the voltage on FB_ reaches 94% of the regulation threshold, the full output current of the LDO controller is permitted. When an LDO is activated, the respective DRV_ is pulled up from GND with a typical soft-start current of 100A. The soft-start current limits the slew of the output voltage and also limits the initial spike of current that the drain of the external n-MOSFET receives. The size of the compensation capacitor (CC) limits the slew rate (see Figure 3). This slew rate is equal to (100 / CC)mV/ms, where CC is in F. The maximum drain current during startup is the ratio of COUT_ to CC multiplied by the softstart current of 100A.
The maximum input voltage to the drain of the n-MOSFET is a function of the breakdown voltage and the thermal conditions during operation. The breakdown voltage from drain to source is normally provided in the MOSFET data sheet. The theoretical maximum input voltage is the set output voltage plus the breakdown voltage. The thermal constraint is usually the largest concern when discussing maximum input voltage. Details on calculating this value are covered in the Power MOSFET Selection section. The MOSFET package and thermal relief on the board are the largest contributors to removing heat from the n-MOSFET. Since output voltage is normally set and maximum output current is fixed, the input voltage becomes the only variable that determines the maximum power dissipated. Thus, the maximum input voltage is limited by the power capability of the n-MOSFET, if it is less than the breakdown voltage, which is most often the case. Ensure input capacitors handle the maximum input voltage. During a power-up sequence where VDD and EN_ rise before the input to the drain of the n-MOSFET, the MAX8563/MAX8564 drive DRV_ high but the output does not rise. As DRV_ rails and VFB_ is still below 80% of the regulation voltage, the MAX8563/MAX8564 assume that an output short-circuit fault is present and shut down that regulator. To avoid this error condition, connect a resistordivider from VDD to IN_ with the middle node connected to the respective EN_ (see Figure 4). Use the following equations to calculate the resistor values. When VIN_ is off or at a low-voltage state: RE 0.7 > x VDD - VIN _ + VIN _ RE + RD
(
)
Input Voltage (Drain Voltage of the External n-MOSFET)
The minimum input voltage to the drain of the n-MOSFET is a function of the desired output voltage and the dropout voltage of the n-MOSFET. Details on calculating this value are covered in the Power MOSFET Selection section.
When VIN_ is on or at a high-voltage state: RE 1.3 < x VDD - VIN _ + VIN _ RE + RD
(
)
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1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers MAX8563/MAX8564
VDD
MAX8563 MAX8564
EN_
RD
RE IN_
The POK_ is an open-drain output that provides the status of the output voltage and pulls low depending upon circuit conditions. During startup, once the FB_ reaches the POK_ threshold, the POK_ signal goes high. The POK_ threshold has 30mV of hysteresis. When the output voltage drops 12% below the nominal regulated voltage, POK_ pulls low. All POK_ outputs pull low when UVLO is activated or when the internal VL regulator and reference are not ready.
Output Undervoltage and Overload Protection
When an overload event or short circuit occurs, the device that is most vulnerable is the external n-MOSFET. The MAX8563/MAX8564 monitor the output voltage to protect the MOSFET. When DRV_ is at its maximum voltage and the output voltage drops below 80% but is still greater than 60% of its nominal voltage for more than 50s, the MAX8563/MAX8564 shut down that particular regulator output by pulling DRV_ to GND. Note that there is an additional inherent delay in turning off the MOSFET. The delay is a function of the compensation capacitor and the MOSFET. If the output recovers to greater than 80% within 50s, it is not considered to be in overload and no action is taken. When the output voltage drops below 60% of its nominal voltage, the MAX8563/ MAX8564 immediately shut down that particular regulator output by pulling DRV_ to GND. To restart that particular LDO, VDD must be recycled below the UVLO or the corresponding EN_ must be recycled. The overload protection is shown in the Typical Operating Characteristics.
Figure 4. Voltage-Divider on EN_
Set RD = 100k. The above equations also assume that VDD > VIN_ > 1V when VIN_ is on or at a high-voltage state, and that VDD > 3V. Example: Connect 100k from EN to VDD and 4k from EN_ to IN_. Thus, when VDD = 12V and VIN_ = 0V, then VEN_ = 0.46V. When VDD = 12V and VIN_ = 1.2V, then VEN_ = 1.6V. Alternately, to avoid fault shutdown due to the delay of VIN relative to VDD, pull EN_ low with a separate control logic and only drive high when VIN reaches a steadystate value.
Output Voltage
The output voltage range at the source of the n-MOSFET is from 0.5V to 3.3V when VDD is 12V and from 0.5V to 1.8V when VDD is 5V. The maximum output voltage is a function of the minimum gate-to-source voltage (VGS) of the MOSFET and VDD. The external n-MOSFET contains a parasitic diode from source to drain. If the output is ever anticipated to exceed the input, current flows from source to drain. If this is undesirable, external protection is needed. A simple solution is the placement of a diode in series, from IN_ to the drain of the n-MOSFET, so that reverse current is not possible. Due to the forward-voltage drop of the diode, the maximum output voltage is reduced and additional power is consumed in the diode.
Design Procedure
Output Voltage Setting
The minimum output voltage for each controller of the MAX8563/MAX8564 is typically 0.5V. The maximum output voltage is adjustable up to 3.3V with VDD = 12V, and up to 1.8V with VDD = 5V. To set the output voltage, connect the FB_ pin to the center of a voltagedivider between OUT_ and GND (Figure 5). The resistor-divider current should be at least 1mA per 1A of maximum output current; i.e., for a 3A maximum output current, set the resistor-divider bias current to 3mA. IOUT(MIN) IOUT(MAX) 1000
Enable and POK
The MAX8563/MAX8564 have independent enable control inputs (EN1, EN2, and EN3). Drive EN1 high to enable output 1. Drive EN2 high to enable output 2. Drive EN3 high to enable output 3. When EN_ is driven low, the corresponding DRV_ is internally pulled to GND and POK_ is internally pulled low.
RB
VFB VFB 500 = 1000 x = IOUT(MIN) IOUT(MAX) IOUT(MAX)
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1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers MAX8563/MAX8564
V RA = RB x OUT - 1 = RB x (2 x VOUT - 1) VFB
OUT_
To set the output voltage to 0.5V, disconnect RB from FB_ and connect it to OUT_; this change maintains the minimum load requirement on the output. In this case, RA can vary from 1k to 10k.
MAX8563 MAX8564
FB_
RA
RB
Input and Output Capacitor Selection
The input filter capacitor aids in providing low input impedance to the regulator and also reduces peak currents drawn from the power source during transient conditions. Use a minimum 2.2F ceramic capacitor from IN_ (drain of the external pass n-MOSFET) to GND (see Figures 1 and 2). If large line transients or load transients are expected, increase the input capacitance to help minimize output voltage changes. The output filter capacitor and its equivalent series resistance (ESR) contribute to the stability of the regulator (see the Stability Compensation section) and affect the load-transient response. If large step loads (no load to full load) are expected, and a very fast response (less than a few microseconds) is required, use a 100F, 18m POSCAP for the output capacitor. If a larger capacitance is desired, keep the capacitance ESR product (COUT x RESR) in the 1s to 5s range. If the application expects smaller load steps (less than 50% of full load), then use a 6.8F ceramic capacitor or larger per ampere of maximum output current. This option reduces the size and cost of the regulator circuit. Note that some ceramic dielectrics exhibit large capacitance variation with temperature. Use X7R or X5R dielectrics to ensure sufficient capacitance at all operating temperatures. Tantalum and aluminum capacitors are not recommended.
Figure 5. Adjustable Output Voltage
current (load current) is the maximum voltage dropout across the MOSFET, VDS_MIN. Make sure that VDS_MIN meets the condition below to avoid entering dropout, where output voltage starts to decrease and any ripple on the input also passes through to the output. VIN_MIN > VDS_MIN + VOUT where VIN_MIN is the minimum input voltage at the drain of the MOSFET. VDS_MIN has a positive temperature coefficient; therefore, the value of VDS_MIN at the highest operating junction temperature should be used. For thermal management, the maximum power dissipation in the MOSFET is calculated by: PD = (VIN_MAX - VOUT) x IOUT_MAX The MOSFET is typically in an SMT package. Refer to the MOSFET data sheet for the PC board area needed to meet the maximum operating junction temperature required.
Stability Compensation
Connect a resistor, RC, and a capacitor, CC, in series from the DRV_ pin to GND. The values of the compensation network depend upon the external MOSFET characteristics, the output current range, and the programmed output voltage. The following parameters are needed from the MOSFET data sheet: the input capacitance (CISS at VDS = 1V), the typical forward transconductance (g FS ) and the current at which g FS was measured (IDFS). Calculate the transconductance of the FET at the maximum load current (IOUT_MAX): gC(MAX) = gFS x IOUT _ MAX IDFS
Power MOSFET Selection
MAX8563/MAX8564 use an n-channel MOSFET as the series pass transistor instead of a p-channel MOSFET to reduce cost. The selected MOSFET must have a gate threshold voltage that meets the following criteria: VGS_MAX VDD - VOUT_ where VDD is the controller bias voltage, and VGS_MAX is the maximum gate voltage required to yield the onresistance (RDS_ON) specified by the manufacturer's data sheet. RDS_ON multiplied by the maximum output
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1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers MAX8563/MAX8564
For the best transient response in applications with large step loads (see the Input and Output Capacitor Selection section for output capacitance requirements), use the following equations to select the compensation components:
0.16 x VOUT x COUT x gC(MAX) x gC(MAX) x RESR + 1 CC = 2 gC(MAX) x VOUT + IOUT _ MAX gC(MAX) = 30S x 1.5A = 12.4S 8.8A
(
(
RC = 59 x
VOUT x COUT gC(MAX) x RESR + 1
CC x gC(MAX) x VOUT + IOUT _ MAX
(
(
)
)

CC = 0.16 x
-
12.4S x 1.5V x 100F x 12.4S x 18m + 1
(12.4S
x 1.5V + 1.5A)
2
-
CISS
2500pF = 0.90F, use 1F.
)
RC = 59 x
7.5V x 100F x (12.4S x 18m + 1) 1F(12.4S x 1.5V + 1.5A)
)
= 599.4 , use 620.
PC Board Layout Guidelines
where COUT is the output capacitance and RESR is the ESR of COUT. To use a low-cost ceramic capacitor (see the Input and Output Capacitor Selection section for load-transient response characteristics), use the following equations to select the compensation components: CC = Due to the high-current paths and tight output accuracy required by most applications, careful PC board layout is required. An evaluation kit (MAX8563EVKIT) is available to speed design. It is important to keep all traces as short as possible to maximize the high-current trace dimensions to reduce the effect of undesirable parasitic inductance. The MOSFET dissipates a fair amount of heat due to the high currents involved, especially during large input-to-output voltage differences. To dissipate the heat generated by the MOSFET, make power traces very wide with a large amount of copper area. An efficient way to achieve good power dissipation on a surface-mount package is to lay out copper areas directly under the MOSFET package on multiple layers and connect the areas through vias. Use a ground plane to minimize impedance and inductance. In addition to the usual high-power considerations, here are four tips to ensure high output accuracy. * Ensure that the feedback connection to COUT_ is short and direct. * Place the feedback resistors next to the FB pin. * Place RC and CC next to the DRV_ pin. * Ensure FB_ and DRV_ traces are away from noisy sources to ensure tight accuracy.
(
COUT x gC(MAX) gC(MAX) x VOUT + IOUT _ MAX COUT CC x gC(MAX)
)
-
CISS
RC = 15 x
Example OUTPUT 1 of Figure 1 is used in this example. Table 1 shows the values required to calculate the compensation. The values were taken from the appropriate data sheets and Figure 1.
Table 1. Parameters Required to Calculate Compensation
PARAMETER MOSFET CISS MOSFET GFS VOUT1 IOUT_MAX COUT1 RESR CONDITIONS VDS = 1V IDFS = 8.8A Figure 1 Figure 1 Figure 1 Figure 1 VALUE 2500 30 1.5 1.5 100 18 UNITS pF S V A F m
12
______________________________________________________________________________________
1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers MAX8563/MAX8564
Pin Configurations
TOP VIEW
DRV1 1 FB1 2 EN1 3 POK1 4 GND 5 N.C. 6 DRV3 7 FB3 8 16 VDD 15 DRV2 14 FB2
MAX8563
13 EN2 12 POK2 11 N.C. 10 POK3 9 EN3
DRV1 1 FB1 EN1 POK1 GND 2 3 4 5
10 VDD 9 DRV2 FB2 EN2 POK2
MAX8564
8 7 6
QSOP
MAX
Chip Information:
TRANSISTOR COUNT: 1801 PROCESS: BiCMOS
______________________________________________________________________________________
13
1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers MAX8563/MAX8564
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
14
______________________________________________________________________________________
1%, Ultra-Low Output Voltage, Dual and Triple Linear n-FET Controllers
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
10LUMAX.EPS
MAX8563/MAX8564
e
10
4X S
10
INCHES MAX DIM MIN 0.043 A 0.006 A1 0.002 A2 0.030 0.037 D1 0.120 0.116 0.118 D2 0.114 E1 0.116 0.120 0.118 E2 0.114 0.199 H 0.187 L 0.0157 0.0275 L1 0.037 REF b 0.007 0.0106 e 0.0197 BSC c 0.0035 0.0078 0.0196 REF S 0 6
MILLIMETERS MAX MIN 1.10 0.15 0.05 0.75 0.95 3.05 2.95 2.89 3.00 3.05 2.95 2.89 3.00 4.75 5.05 0.40 0.70 0.940 REF 0.177 0.270 0.500 BSC 0.090 0.200 0.498 REF 0 6
H 0 0.500.1 0.60.1
1
1
0.60.1
TOP VIEW
BOTTOM VIEW
D2 GAGE PLANE A2 A b A1 D1
E2
c
E1 L1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 10L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0061
1 1
I
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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